1. Field of the Invention
The present invention related to semiconductor devices and, more particularly, to a seal ring structure for an integrated circuit that is capable of reducing substrate noise coupling.
2. Description of the Prior Art
Advances in fabrication technology have enabled entire functional blocks, which previously had been implemented as plural chips on a circuit board, to be integrated onto a single IC. One particularly significant development is mixed-signal circuits, which combine analog circuitry and digital logic circuitry onto a single IC.
However, a major technical hurdle to implementing mixed-signal circuits has been the coupling of noise between different portions of the IC, for example, from the digital to the analog portions. Ordinarily, an integrated circuit chip includes a seal ring used to protect it from moisture degradation or ionic contamination. Typically, the seal ring is made of a stack of metal and contact/via layers and is manufactured step by step as sequential depositions of insulators and metals in conjunction together with the fabrication of the integrated circuit elements.
It has been found that the noise, such as digital noise, which, for example, may be originated from a digital power signal line such as VDD or signal pad of a digital circuit, propagates through the seal ring and adversely affects the performance of the sensitive analog and/or RF circuit.
FIG. 1 is a schematic, cross-sectional diagram showing a seal ring structure 524 according to the related art. As shown in FIG. 1, the seal ring structure 524 is divided into two portions including a first portion 524a and a second portion 524b spaced apart from the first portion 524a. Between the first portion 524a and the second portion 524b, there is provided a chipped region 525. The second portion 524b comprises a conductive rampart 701 that is made of a stack of metal layers (M1 and M2) and contact/via layers (C and V1). The second portion 524b further comprises a P+ region 702 situated under the conductive rampart 701 and a P well 704 under the P+ region 702. The P+ region 702 and the P well 704 are isolated from the P+ region 602 and the P well 604 under the conductive rampart 601 of the first portion 524a by a shallow trench isolation (STI) structure 760.